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Programmer’s Reference Manual 31
Intel
®
High Definition Audio Controller Registers (D27:F0)
1.1.37 PVCCAP2 — Port VC Capability Register 2
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 108h–10Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
1.1.38 PVCCTL — Port VC Control Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 10Ch–10Dh Attribute: RO
Default Value: 0000h Size: 16 bits
1.1.39 PVCSTS—Port VC Status Register
(Intel
®
High Definition Audio Controller—D27:F0)
Address Offset: 10Eh-10Fh Attribute: RO
Default Value: 0000h Size: 16 bits
Bit Description
31:24
VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration table is not
present.
23:8 Reserved.
7:0
VC Arbitration Capability — RO. Hardwired to 0. These bits are not applicable since the Intel
®
High
Definition Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1
register.
Bit Description
15:4 Reserved.
3:1
VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However, these bits are
not applicable since the Intel
®
High Definition Audio controller reports a 0 in the Low Priority
Extended VC Count bits in the PVCCAP1 register.
0 Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not present.
Bit Description
15:1 Reserved.
0 VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not present.