Filter
Top Products
Programmer’s Reference Manual 119
Intel® High Definition Audio BIOS Considerations
; (bits 31:28) respresents the codec address (CAd).
; c. Set bits 1:0 of the IRS register at AZBAR+68h[1:0]
; d. Poll ICS register bits at AZBAR+68h[1:0] until they return 10b
indicating
; the verb has been sent to the codec and response data from codec is
now valid.
; e. Read IR register at AZBAR+64h, the dword data is the VendorID/
Device
; ID value returned by the codec
;----------------------------------------------------------------------------
; a. Poll the ICB bit in the ICS register at AZBAR+68h[0] until it returns 0
push cx
xor cx, cx ; 64K cycles
PollICBBit:
test word ptr es:[ebx+HDAudio_MMIO_ICS],
HDAudio_MMIO_ICS_ICB
jz ICBBitClear ; Poll ICB bit until it returns 0
loop PollICBBit
; Add error handling code here
; When timeout occurs, reset link per audio driver team request
and byte ptr es:[ebx+HDAudio_MMIO_GCTL], NOT
HDAudio_MMIO_GCTL_CRST
or byte ptr es:[ebx+HDAudio_MMIO_GCTL],
HDAudio_MMIO_GCTL_CRST
ICBBitClear:
pop cx
; b. Write verb c00F0000h (dword) to the IC register at AZBAR+60h;
where 'c'
; (bits 31:28) respresents the codec address (CAd).
mov eax, ecx
shl eax, 28
or eax, 000F0000h
mov dword ptr es:[ebx+HDAudio_MMIO_IC], eax ; Write the verb
; c. Set bits 1:0 of the IRS register at AZBAR+60h[1:0]
or word ptr es:[ebx+HDAudio_MMIO_ICS], BIT1+BIT0 ; Send the
command
; d. Poll ICS register bits at AZBAR+68h[1:0] until they return 10b
indicating