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FX Series Programmable Controlers Applied Instructions 5
5-37
5.4.5 SFTR (FNC 34)
Operation:
The instruction copies n
2
source devices to a bit
stack of len
g
th n
1
. For ever
y
new addition of n
2
bits,
the existin
g
data within the bit stack is shifted n
2
bits
to the ri
g
ht. An
y
bit data movin
g
to a position
exceedin
g
the n
1
limit is diverted to an overflow area.
The bit shiftin
g
operation will occur ever
y
time the
instruction is processed unless it is modified with
either the pulse suffix or a controlled interlock.
5.4.6 SFTL (FNC 35)
Operation:
The instruction copies n
2
source devices to a bit
stack of len
g
th n
1
. For ever
y
new addition of n
2
bits,
the existin
g
data within the bit stack is shifted n
2
bits
to the left. An
y
bit data movin
g
to a position
exceedin
g
the n
1
limit is diverted to an overflow area.
The bit shiftin
g
operation will occur ever
y
time the
instruction is processed unless it is modified with
either the pulse suffix or a controlled interlock.
Mnemonic Function
Operands
Program steps
SD
n
1
n
2
SFTR
FNC 34
(
Bit shift
ri
g
ht)
The status of the
source devices are
copied to a
controlled bit stack
movin
g
the existin
g
data to the ri
g
ht
X, Y, M, S Y, M, S K,H,
Note:
FX users:
n
2
≤
n
1
≤
1024
FX
0
,FX
0N
users:
n
2
≤
n
1
≤
512
SFTR,SFTRP:
9 steps
Mnemonic Function
Operands
Program steps
SD
n
1
n
2
SFTL
FNC 35
(
Bit shift
left)
The status of the
source devices are
copied to a
controlled bit stack
movin
g
the existin
g
data to the left
X, Y, M, S Y, M, S K,H,
Note:
FX users: n
2
≤
n
1
≤
1024
FX
0
,FX
0N
users:
n
2
≤
n
1
≤
512
SFTL,SFTLP:
9steps
X6
SFTR
X 0
M 0
K 16
K 4
[S] [D] [n1] [n2]
X3 X2 X1 X0
M15M14M13M12 M11M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
X7
SFTL
X 10
Y 0
K 12
K 3
[S] [D] [n1] [n2]
Y2 Y1 Y0
X12
X11X10
Y5 Y4 Y3
Y10 Y7
Y6
Y13 Y12 Y11