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FX Series Programmable Controlers Applied Instructions 5
5-70
5.7.3 ABSD (FNC 62)
Operation:
This instruction
g
enerates a variet
y
of output
patterns (there are n number of addressed
outputs) in response to the current value of a
selected counter, S2.
Points to note:
a) The current value of the selected counter (S2) is compared a
g
ainst a user defined data
table. This data table has a head address identified b
y
operand S1. S1should alwa
y
s have
an even device number.
b) For each destination bit (D) there are two consecutive values stored in the data table. The
first allocated value represents the event number when the destination device (D) will be
turned ON. The second identifies the reset event. The data table values are allocated as a
consecutive pair for each sequential element between D and D+n.
c) The data table has a len
g
th equal to 2
×
n data entries. Dependin
g
on the format of the data
table, a sin
g
le entr
y
can be one data word such as D300 or a
g
roup of 16 bit devices e.
g
.
K4X000.
d) Values from 0 to 32,767 ma
y
be used in the data table.
e) The ABSD instruction ma
y
onl
y
be used
ONCE
.
f) FX CPU’s ver 3.07 or
g
reater and FX2C units have double word option on this instruction.
From the example instruction and the data table below, the followin
g
timin
g
dia
g
ram for
elements M0 to M3 can be constructed.
Mnemonic Function
Operands
Program steps
S
1
S
2
Dn
ABSD
FNC 62
(Absolute
drum
sequencer)
Generates
multiple output
patterns in
response to
counter data
KnX, KnY,
KnM, KnS,
(in
g
roups
of 8)
T, C, D
C Y,M,S
Note:
n consec-
utive
devices
are used
K,H
Note:
n
≤
64
ABSD:
9 steps
DABSD:
17 steps.
see f).
Note: Hi
g
h speed
counters are not
allowed
X0
C 0D300 M 0
[ S1 ] [ S2 ] [ D ]
K 4
[ n ]
ABSD
D300 - 40
When counter S2 e
q
uals the
value below, the destination
device D is
Assi
g
ned
destination
device D
D302 - 100
D304 - 160
D306 - 240
D301 - 140
D303 - 200
D305 - 60
D307 - 280
M0
M1
M2
M3
turned ON turned OFF
M 0
M 1
M 2
M 3
40 140
100 200
60 160
240 280
0 180 360
Count value
ON
OFF