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FX Series Programmable Controllers Execution Times And Instructional Hierarchy 7
7-13
The followin
g
table identifies an 'overlap-pin
g
relationship'. This means the secondar
y
pro
g
ram
construction starts within the complete operatin
g
boundaries of the primar
y
pro
g
ram construction but
finishes outside of the primar
y
construction, e.
g
.:
Enters a state as if the DI instruction was missin
g
. An error is not
g
enerated.
The first occurrence of either an FEND or the END instruction takes priorit
y
. This would
then end the pro
g
ram scan prematurel
y
.
The sequence will not process as expected, e.
g
.:
Primary
Program
Construction
Secondary program construction
MC-MCR CJ - P EI - DI
FOR -
NEXT
STL -
RET
P - SRET I - IRET
FEND -
END
MC - MCR
-
(
6607
)
-
(
6605
)
-
(
6606
)
-
(
6606
)
-
(
6608
)
CJ - P
EI - DI
FOR - NEXT
-
(
6607
)
¬
-
(
6601
)
-
(
6607
)
-
(
6607
)
-
(
6607
)
STL - RET
-
(
6605
)
-
(
6607
)
-
(
6606
)
-
(
6606
)
-
(
6605
)
P - SRET
-
(
6608
)
-
(
6607
)
-
(
6605
)
-
(
6606
)
-
(
6606
)
-
(
6709
)
I - IRET
-
(
6606
)
-
(
6607
)
-
(
6606
)
-
(
6606
)
-
(
6606
)
-
(
6606
)
FEND - END
-
(
6608
)
-
(
6601
)
-
(
6607
)
-
(
6605
)
-
(
6709
)
-
(
6709
)
0 - FEND
-
(
6608
)
-
(
6607
)
-
(
6605
)
-
(
6709
)
-
(
6606
)
0 - END
(no FEND)
-
(
6608
)
-
(
6601
)
-
(
6607
)
-
(
6605
)
-
(
6709
)
-
(
6606
)
FOR
EI
DI
NEXT
Primary
program construction
Secondary
program construction
FOR
NEXT
FOR
NEXT
Desired
FOR
NEXT
FOR
NEXT
Actual
Operating
boundries