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Bits 7: Reserved
Bit 6: NEW_RX_MIN_MASK is set to suppress the new RX Min Error from setting the EOS_D_SUM
Summary Interrupt bit. This interrupt mask bit does not affect the corresponding interrupt event
bit.
Bit 5: NEW_RX_MAX_MASK is set to suppress the new RX Max Error from setting the EOS_D_SUM
Summary Interrupt bit. This interrupt mask bit does not affect the corresponding interrupt event
bit.
Bit 4: NEW_RX_OOS_MASK is set to suppress the new RX Out of Sync Error from setting the
EOS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding
interrupt event bit. This bit is a fixed one in LAPS mode.
Bit 3: NEW_RX_FORM_DEST_MASK is set to suppress the new RX Format/Destination Error from
setting the EOS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the
corresponding interrupt event bit.
Bit 2: NEW_RX_FIFO_UR_MASK is set to suppress the new RX FIFO Underrun Error from setting the
EOS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding
interrupt event bit.
Bit 1: NEW_RX_FIFO_OF_MASK is set to suppress the new RX FIFO Overflow Error from setting the
EOS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding
interrupt event bit.
Bit 0: NEW_RX_FCS_HEC_MASK is set to suppress the new RX FCS and HEC Error from setting the
EOS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding
interrupt event bit.
ADDR = 0x1ED: Ethernet Receive Interrupt Mask
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_ NEW_RX_
MIN_ MAX_ OOS_ FORM_ FIFO_UR_ FIFO_OF_ FCS_HEC_
MASK MASK MASK DEST_MASK MASK MASK MASK
R/W — R/W R/W R/W R/W R/W R/W R/W
Value 0 111 1 1 1 1
after
reset