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3. Functional Description
3.1 Introduction
The HDMP-3001 performs full-
duplex mapping of Ethernet
frames into a SONET STS-3c /
SDH STM-1 payload using the
LAPS or GFP protocol. All
SONET/SDH framing functions
are included. A TOH
interface provides direct add/drop
capability for E1, E2, F1, and both
Section and Line DCC channels.
SONET or SDH mode is selected
during initial configuration.
By default, the HDMP-3001 oper-
ates in LAPS mode. LAPS is a
HDLC-compatible protocol. The
LAPS transmit processing in-
cludes packet framing,
inter-frame fill, payload scram-
bling (X
43
+1), transparency
processing (byte stuffing) and 32-
bit CRC generation. The receive
LAPS processing provides for the
extraction of LAPS frames, trans-
parency removal, descrambling,
header and FCS checking.
The HDMP-3001 can also be con-
figured to operate in GFP mode.
The GFP transmit processing in-
cludes the insertion of framed
packet framing, idle frame inser-
tion, payload scrambling (X
43
+1)
and 32-bit CRC generation. The
receive GFP processing provides
for the extraction of GFP frames,
descrambling, header and FCS
error checking.
A robust set of performance
counters and status/control regis-
ters for performance monitoring
via the external microprocessor
or MDIO is provided.
The SONET/SDH line side con-
sists of an 8-bit parallel interface
which operates at 19.44 MHz.The
device is typically connected to a
parallel-to-serial converter, which
is in turn connected to an optical
transceiver for interfacing to a
fiber. The Ethernet interface is a
standard MII interface which op-
erates at 25 MHz (4-bit). Only 100
Mb/s full-duplex operation is sup-
ported, i.e. collisions are not
supported. This device can be
controlled through either a micro-
processor port or a two-wire
MDIO (MII Management)
port. The complete register map
can be accessed from both these
ports. Additionally, the initial con-
figuration can be automatically
downloaded from an EEPROM
which is useful in designs without
on-board intelligence.
3.2 Interface Descriptions
3.2.1 Microprocessor Interface
The interface consists of eight
data bits, nine address bits, three
control signals and one acknowl-
edge signal. Through this
interface the HDMP-3001 internal
register map can be accessed.
Only one of the microprocessor,
MII Management or EEPROM
ports can be active at any one
time. Hence, in the rare cases
where more than one port is used,
care has to be taken not to have
more than one port active simulta-
neously.
3.2.2 MII Management Interface
The MII Management interface is
a standard port for Ethernet PHYs
and is defined in the IEEE 802.3
specification. It is a two wire in-
terface that allows access to
thirty-two sixteen-bit data regis-
ters. These are defined in the MII
Management memory map. Six-
teen of the data registers are
defined by the IEEE specification
and sixteen are left for vendor
specific purposes. Two of the ven-
dor specific registers in the
HDMP-3001 are used to enable
access to the internal chip regis-
ters through indirect addressing.
One of the vendor specific regis-
ters is used to shadow the
frequently polled master alarm
register.
3.2.3 EEPROM Interface
This port operates in master mode
only, i.e. the HDMP-3001 cannot
be accessed through this port.
One use of this port is to config-
ure the chip in stand-alone
applications. Another use is to
assign unique PHY addresses to
cascaded HDMP-3001 ICs when
they are controlled through the
MDIO port.
If enabled, this port is automati-
cally activated after reset to load
the HDMP-3001 configuration
from an EEPROM. The complete
address space of the HDMP-3001,
511 to 0, is filled with the data
from EEPROM addresses 511 to 0.
EEPROMs like Philips’
PCF8594C-2, Fairchild’s
NM24C02U or Atmel’s AT24C04
are supported. The EEPROM de-
vice address should be set to zero.
The SCL clock rate is just under
100 kHz. It takes a little under 300
ms for the EEPROM to load, so
during this time the microproces-
sor and MII Management ports
must stay inactive.
3.2.4 MII Interface
This interface is a 100 Mb/s full-
duplex Ethernet MII interface as
defined by IEEE 802.3. It operates
at 25 MHz. At power-up the MII
Isolate bit in the register map is
active, which sets all output pins
in this interface to high impedance
and ignores all MII inputs.