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8.2 Microprocessor Bus Timing - Read Cycle.
Figure 30. Microprocessor Read Cycle Timing.
* RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. This
adds an additional delay of between one and two microprocessor clock cycles.
VALID
t
7
t
10
t
9
INVALID
VALID
CAPTURED
Hi - Z
Hi - Z
Hi - Z
Hi - Z
A[8:0]
CSB
WRB
RDB
D[7:0] (IN)
D[7:0] (OUT)
RDYB
*
GPIO[15:0]
t
11
t
12
t
1
t
8
t
5
BIDIR
OUTPUTS
INPUTS