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5.5 Ethernet Transmit Registers
ADDR = 0x180: GFP/LAPS control
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved Reserved TX_SCR_ TX_FCS_ TX_FCS_
INH CORR INH
R/W — ——— — R/W R/W R/W
Value 0000 000 0
after
reset
Bits 7-3: Reserved
Bit 2: TX_SCR_INH is set to inhibit the Ethernet TX scrambling (X
43
+ 1). GFP DC
balancing of the core header is still performed.
Bit 1: TX_FCS_CORR is set to force corrupted FCS fields to be sent.
Bit 0: TX_FCS_INH is set to inhibit the TX FCS (32-bit CRC) field from being transmitted.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name TX_ADR_DPSP[7:0]
R/W R/W
Value 0x04
after
reset
ADDR = 0x181: Transmit ADR/DPSP Byte
Bits 7-0: TX_ADR_DPSP[7:0] specifies the Address byte for LAPS mode and the {DP, SP} Byte for GFP
mode. This byte will be sent out in the encapsulated LAPS or GFP frame from the Ethernet side to
the SONET/SDH side if the TX_ADR_INH or TX_EXT_HDR_INH bit is not set, respectively. The
default value is 0x04 for LAPS, since LAPS is the default mode. For GFP mode, this
register must be programmed.