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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved Reserved LO_IFG_WATER_MARK[10:8]
R/W —— ——— R/W
Value 00 000 0x2
after
reset
ADDR = 0x1C7: Low Inter-Frame-Gap Water Mark
Bits 7-3: Reserved
Bits 2-0: LO_IFG_WATER_MARK[10:8] are the three MSBs of the previous register.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved NORMAL_IFG[4:0]
R/W —— ——R/W
Value 0 0 0 0 0x0C
after
reset
ADDR = 0x1C8: Normal Inter-Frame-Gap
Bits 7-5: Reserved
Bits 4-0: NORMAL_IFG[4:0] specifies the Normal Inter-Frame-Gap which is used by the MII RX interface
to insert the minimum number of idle cycles between two MAC frames sent out onto the MII RX
bus. This value is used when the INFO FIELD RX FIFO Controller sets the IFG Selection Mode
(IFG_SEL) to Normal-IFG and sends it to MII RX interface. When the number of bytes in the RX
FIFO becomes less than or equal to the Low Inter-Frame-Gap Water Mark, IFG_SEL is set to zero
for Normal-IFG. At power-up, IFG_SEL is set to zero for Normal-IFG selection. This value remains
zero until the number of bytes in the RX FIFO becomes greater than or equal to the programmable
High Inter-Frame-Gap Water Mark.