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Signal name Pin # Type(I/O) Signal description
TX_FRAME_SFP 125 O TRANSMIT FRAME POSITION OUTPUT INDICATOR: Frame position
indication signal is active high and indicates the SONET frame
position on the TX_DATA [7:0] bus. Updated on the rising edge of
TX_SONETCLK. This signal is also used for the outer board to start
sending the first bit (MSB) of the serial data E1, E2, F1, SDCC,
and LDCC.
TX_SONETCLK 133 I TRANSMIT SONET CLOCK: TX_SONETCLK is the transmit output
clock to the line side, and provides timing for the transmit data
bus and frame position indication outputs. This clock should be
19.44 MHz ± 20 ppm.
LOC_TX 115 O Loss of SONET_TX clock.
LOC_RX 116 O Loss of SONET_RX clock.
Signal name Pin # Type(I/O) Signal description
SYS_25M_CLK 88 I Drives the two MII clocks in PHY mode, TX_CLK and
RX_CLK. It is also used to monitor the TX_SONETCLK
and RX_SONETCLK.
The requirement for this clock is 25 MHz ±100 ppm.
P_TX_CLK_M_RX_CLK 104 I/O (Int. PU) PHY mode: transmit clock output. Derived from
SYS_25M_CLK.
MAC mode: receive clock input. Nominally 25 MHz.
P_TXD_M_RXD[0] 108 I PHY mode: transmit data nibble.
P_TXD_M_RXD[1] 107 MAC mode: receive data nibble.
P_TXD_M_RXD[2] 106
P_TXD_M_RXD[3] 105
P_TX_EN_M_RX_DV 109 I PHY mode: transmit data enable.
MAC mode: receive data valid.
P_RX_CLK_M_TX_CLK 93 I/O (Int. PU) PHY mode: receive clock output. Derived from
SYS_25M_CLK.
MAC mode: transmit clock input. Nominally 25 MHz.
P_RXD_M_TXD[0] 97 O (T/S) PHY mode: receive data nibble.
P_RXD_M_TXD[1] 96 MAC mode: transmit data nibble.
P_RXD_M_TXD[2] 95
P_RXD_M_TXD[3] 94
P_RX_DV_M_TX_EN 98 O (T/S) PHY mode: receive data valid.
MAC mode: transmit data enable.
P_RX_ER_M_TX_ER 103 O (T/S) PHY mode: receive error.
MAC mode: transmit error.
P_TX_ER_M_RX_ER 112 I PHY mode: transmit error.
MAC mode: receive error.
Table 2. MII Interface Pins Description
(continues)