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Address Bit Type Bit Name Default value Description
8 R Extended Status Fixed 0 No extended status information in
register 15.
7 R Reserved Fixed 0
6 R MF Preamble Suppression Fixed 0 PHY does not allow preamble to be
suppressed in management frames.
5 R Auto-Negotiation Complete Fixed 0 Not supported.
4 R Remote Fault Fixed 0 Not supported.
3 R Auto-Negotiation Ability Fixed 0 Cannot auto-negotiate.
2 R Link Status 0 Reflects the SONET status. When
SONET is up, this bit is set.
1 R Jabber Detect Fixed 0
0 R Extended Capability Fixed 1 Registers 2-10 supported.
2 15-0 R PHY Identifier Fixed 00C3h Bits 3 to 18 of the IEEE assigned
Organizationally Unique Identifier.
3 15-10 R PHY Identifier Fixed 010011 Bits 19 to 24 of the IEEE assigned
Organizationally Unique Identifier.
9-4 Fixed 000010 Manufacturer’s Model Number.
3-0 Fixed 0000 Revision Number.
4-10 15-0 R Extended Capabilities Not supported.
11-14 15-0 R Reserved Unused. Unused.
15 15-0 R Extended Status Not supported.
16 15-9 R Unused Fixed 0
8-0 R/W Indirect Address 0 Address of the internal chip register to
be written to or read from.
17 15-8 R Unused Fixed 0 The internal chip register bus is 8 bits
wide so these bits are always 0.
7-0 R/W Data 0 Data read from or written to an internal
chip register.
18 15-8 R Unused Fixed 0
7-0 R Master Alarm 0 This is a shadow of the master alarm
chip register.
19-31 15-0 R Vendor Specific Read/ Write Unused
Read/ Write
transactions
ignored, MDIO
in Hi-Z
Read/ Write
transactions
ignored, MDIO
in Hi-Z