Filter
Top Products
81
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name TX_FIFO_THRESHOLD[7:0] (LSB)
R/W R/W
Value 0x88
after
reset
ADDR = 0x184: Transmit FIFO Threshold[7:0] (LSB)
TX_FIFO_THRESHOLD[7:0] specifies the LSB of the TX FIFO Threshold which is used by the
INFO FIELD TX FIFO Controller to determine when it starts to read the data from the TX FIFO.
For frames of which the size is greater than the programmed TX_FIFO_THRESHOLD, the INFO
FIELD TX FIFO Controller begins to read data out of the TX FIFO when the number of bytes of the
portion of the transmitting frame that has been stored into the TX FIFO is equal to or greater than
the programmed TX_FIFO_THRESHOLD. The default value is set to 648 bytes (0x0288). When
Rate Adaptation is used, the threshold value can be lowered.
This register is only used in LAPS mode. In GFP mode transmission starts only when a complete frame is
in the FIFO.
ADDR = 0x185: Transmit FIFO Threshold[10:8] (MSB)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved Reserved TX_FIFO_THRESHOLD[10:8]
(MSB)
R/W — ——— — R/W
Value 0 0 0 0 0 0x02
after
reset
MSBs of the register above.