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APPROX. 2M TX_LDCC_CLK BURSTS
ROW 1
BYTES
ROW 2
BYTES
ROW 3
BYTES
ROW 4
BYTES
ROW 5
BYTES
ROW 6
BYTES
ROW 7
BYTES
ROW 8
BYTES
ROW 9
BYTES
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
TX_FRAME_SFP
TX_SDCC_CLK
TX_SDCC_DATA
TX_LDCC_CLK
TX_LDCC_DATA
TX_LDCC_CLK
TX_LDCC_DATA
Figure 45. Transmit Data Link Clock and Data Alignment
The transmit data link clock and data alignment timing diagram (Figure 45) shows the relationship between
the TX_SDCC_DATA, and TX_LDCC_DATA serial data inputs, and their associated clocks, TX_SDCC_CLK
and TX_LDCC_CLK respectively. TX_SDCC_CLK is a 216 kHz, 50% duty cycle clock that is gapped to
produce a 192 kHz nominal rate that is aligned with TX_FRAME_SFP as shown. TX_LDCC_CLK is a 2.16
MHz, 67%(high)/33%(low) duty cycle clock that is gapped to produce a 576 kHz nominal rate that is aligned
with TX_FRAME_SFP as shown. TX_SDCC_DATA (TX_LDCC_DATA) is sampled on the rising
TX_SDCC_CLK (TX_LDCC_CLK) edge.