Filter
Top Products
53
ADDR=0x009: Mode of Operation
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved ISOLATE_ SONET/SDH PHY/MAC GFP/LAPS
MII
R/W —— — — R/W R/W R/W R/W
Value 000010 0 0
after
reset
Note that this register only should be programmed when STATE_RESET is active.
Bits 7-4: Reserved
Bit 3: ISOLATE_MII is set to isolate the HDMP-3001 chip on the MII bus. When it is set, TX_CLK,
RX_CLK, RX_DV, RX_ER and RXD outputs will be tristated. TXD, TX_EN and TX_ER inputs are
ignored. This bit has the same effect as the MII Management Register ISOLATE in address 0 bit 10.
Bit 2: SONET/SDH: 0 in SONET mode, 1 in SDH mode.
Bit 1: PHY/MAC: 0 in MAC mode, 1 in PHY mode.
Bit 0: GFP/LAPS 0 in LAPS mode, 1 in GFP mode.
ADDR=0x00A: Rx Event Summary Mask
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name TOH_D_SUM Reserved PTR_D_SUM POH_D_SUM Reserved EOS_D_ Reserved Reserved
_MASK _MASK _MASK SUM_MASK
R/W R/W — R/W R/W — R/W ——
Value 10110100
after
reset
Bit 7: TOH_D_SUM_MASK is set to disable TOH_D_SUM interrupt to report to SUM_INT
Bit 6: Reserved
Bit 5: PTR_D_SUM_MASK is set to disable PTR_D_SUM interrupt to report to SUM_INT
Bit 4: POH_D_SUM_MASK is set to disable POH_D_SUM interrupt to report to SUM_INT
Bit 3: Reserved
Bit 2: EOS_D_SUM_MASK is set to disable EoS_D_SUM interrupt to report to SUM_INT
Bits 1-0: Reserved