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ADDR = 0x186: Transmit LAPS mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved TX_ADR_ TX_CNT_ TX_SAPI_ TX_ABORT TX_RA_
INH INH INH _INH INH
R/W ———R/W R/W R/W R/W R/W
Value 0000 000 0
after
reset
Bits 7-5: Reserved
Bit 4: TX_ADR_INH is set to inhibit the insertion of the programmed address byte into the LAPS frame
for test purposes. Instead, the byte is taken from the MII payload.
Bit 3: TX_CNT_INH is set to inhibit the insertion of the programmed control byte into the LAPS frame
for test purposes. Instead, the byte is taken from the MII payload.
Bit 2: TX_SAPI_INH is set to inhibit the insertion of the two programmed SAPI bytes into the LAPS
frame for test purposes. Instead, the bytes are taken from the MII payload.
Bit 1: TX_ABORT_INH is set to inhibit the generation of abort sequence in case an error condition
occurs during Ethernet TX processing.
Bit 0: TX_RA_INH is set to inhibit the generation of the rate adaptation sequence when an underrun
occurs in the TX FIFO. If the abort sequence is also inhibited, the FCS is corrupted.
ADDR = 0x187: Transmit GFP Mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved TX_CORE TX_EXT_ TX_EXT_ TX_TYPE_ TX_TYPE_
_HD_INH HEC_ HDR_INH HEC_ HDR_INH
CORR CORR
R/W ———R/W R/W R/W R/W R/W
Value 0000 000 0
after
reset
Bits 7-5: Reserved
Bit 4: TX_CORE_HD_INH inhibits the insertion of a core header in the payload for test purposes. Idle
packet core headers are always enabled. A state machine reset is required to make changes to
this bit effective. When active, the Type and Extended headers should also be inhibited.
Bit 3: TX_EXT_HEC_CORR corrupts the extended header HEC.
Bit 2: TX_EXT_HDR_INH is set to inhibit the generation of the GFP Frame Payload Extended Header,
which includes the {DP,SP} byte, Spare byte, and LSB and MSB bytes of eHEC. This bit is set to
create a GFP null header.
Bit 1: TX_TYPE_HEC_CORR corrupts the type header HEC.
Bit 0: TX_TYPE_HDR_INH is set to inhibit the insertion of the programmed Type Header and tHEC
bytes for test purposes. Instead, the four bytes are taken from the MII payload.