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ADDR = 0x1A1: Ethernet Transmit Interrupt Mask
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved NEW_TX_ NEW_TX_ NEW_TX_ NEW_TX_
FIFO_UR_ FIFO_OF_ ER_MASK MII_ALIGN
MASK MASK _MASK
R/W — ——— R/W R/W R/W R/W
Value 0000 111 1
after
reset
Bits 7-4: Reserved
Bit 3: NEW_TX_FIFO_UR_MASK is set to suppress the new TX FIFO Underrun Error from setting the
EoS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding
interrupt event bit.
Bit 2: NEW_TX_FIFO_OF_MASK is set to suppress the new TX FIFO Overflow Error from setting the
EoS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding
interrupt event bit.
Bit 1: NEW_TX_ER_MASK is set to suppress the new TX_ER Error from setting the EoS_D_SUM
Summary Interrupt bit. This interrupt mask bit does not affect the corresponding interrupt event
bit.
Bit 0: NEW_TX_MII_ALIGN_MASK is set to suppress the new TX MII Alignment Error from setting
the EoS_D_SUM Summary Interrupt bit. This interrupt mask bit does not affect the corresponding
interrupt event bit.