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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved RX_PRESYNC[3:0]
R/W —— ——R/W
Value 00 000x1
after
reset
ADDR = 0x1D0: Receive Pre-Sync States
Bits 7-4: Reserved
Bits3-0: RX_PRESYNC specifies the number of Pre-Sync states the GFP RX Processor performs before it
transits to the Sync state during the GFP frame delineation process, which finds GFP frames by
checking octet by octet for a correct cHEC for the sequence of the last four octets. Once a correct
cHEC is found, it is assumed that a GFP frame has been found, and the Pre-Sync state is entered.
In the Pre-Sync state, the GFP frame delineation process checks frame by frame for a correct
cHEC. The process repeats until RX_PRESYNC consecutive correct HECs are confirmed, at which
point the process moves to the Sync state. If an incorrect cHEC is found, the process returns to the
Hunt state. The RX_PRESYNC value is the same as the DELTA value specified in the T1X1 GFP
proposal.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name RX_SAPI_L[7:0]
R/W R/W
Value 0x01
after
reset
ADDR = 0x1D1: Receive SAPI LSB
Bits 7-0: RX_SAPI_L[7:0] specifies the expected LSB of the SAPI field when in GFP mode. If
RX_SAPI_CHECK_INH is not set, frames with a non-matching SAPI Field are discarded and the
Form/Dest Error counter is incremented.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name RX_SAPI_H[7:0]
R/W R/W
Value 0xFE
after
reset
ADDR = 0x1D2: Receive SAPI MSB
Bits 7-0: RX_SAPI_H[7:0] is the MSB of the field above.