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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name Reserved Reserved Reserved Reserved Reserved RX_FIFO_THRESHOLD[10:8]
R/W —— ——— R/W
Value 00 000 0x1
after
reset
ADDR = 0x1C3: RX FIFO Transmit Threshold[10:8]
Bits 7-3: Reserved
Bits 2-0: RX_FIFO_THRESHOLD[10:8] are the three MSBs of the previous register.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit name HI_IFG_WATER_MARK[7:0]
R/W R/W
Value 0x00
after
reset
ADDR = 0x1C4: High Inter-Frame-Gap Water Mark
Bits 7-0: HI_IFG_WATER_MARK[7:0] is the LSB of the High Inter-Frame-Gap Water Mark which is
used by the INFO FIELD RX FIFO Controller to determine when to change the IFG Selection Mode
(IFG_SEL) for the MII RX interface from Normal-IFG to Low-IFG. The IFG Selection Mode is used
to control the minimum number of MII clock cycles between consecutive MAC frames sent out on
the MII RX bus from the HDMP-3001 chip. When the number of bytes in the RX FIFO becomes
greater than or equal to the High Inter-Frame-Gap Water Mark, the IFG_SEL is set to one for Low-
IFG. When the number of bytes in the RX FIFO becomes less than or equal to the Low Inter-
Frame-Gap Water Mark, the IFG_SEL is set to zero for Normal-IFG. At power-up, the IFG_SEL
defaults to zero for Normal-IFG selection. This value remains zero until the number of bytes in the
RX FIFO becomes greater than or equal to the programmable High Inter-Frame-Gap Water Mark.
The IFG selection process continues as described above. The default value of
HI_IFG_WATER_MARK is 1536 bytes (0x0600).