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8. Timing Diagrams
8.1 Microprocessor Bus Timing - Write Cycle
Figure 29. Microprocessor Write Cycle Timing.
* RDYB is re-clocked twice by the microprocessor clock in addition to the timing shown. This
adds an additional delay of between one and two microprocessor clock cycles.
VALID
VALID
NEW VALUE
t
1
t
2
t
6
Hi - Z
t
3
t
4
t
5
Hi - Z
Hi - Z
A[8:0]
CSB
WRB
RDB
D[7:0] (IN)
D[7:0] (OUT)
RDYB
*
GPIO[15:0]
BIDIR
OUTPUTS
INPUTS