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Rev. 1.0, 07/01, page 295 of 372
Table 20-4 I
2
C Bus Interface Timing
V
CC
= 3.0 to 5.5 V, V
SS
= 0.0 V, T
a
= –20 to +75°C, unless otherwise indicated.
Test
Values
Reference
Item Symbol Condition Min Typ Max Unit Figure
SCL input cycle time t
SCL
12t
cyc
+ 600 — — ns Figure 20-4
SCL input high width t
SCLH
3t
cyc
+ 300 — — ns
SCL input low width t
SCLL
5t
cyc
+ 300 — — ns
SCL and SDA input
fall time
t
Sf
— — 300 ns
SCL and SDA input
spike pulse removal
time
t
SP
——1t
cyc
ns
SDA input bus-free
time
t
BUF
5t
cyc
——ns
Start condition input
hold time
t
STAH
3t
cyc
——ns
Retransmission start
condition input setup
time
t
STAS
3t
cyc
——ns
Setup time for stop
condition input
t
STOS
3t
cyc
——ns
Data-input setup time t
SDAS
1t
cyc
+20 — — ns
Data-input hold time t
SDAH
0——ns
Capacitive load of
SCL and SDA
c
b
0 — 400 pF
SCL and SDA output
fall time
t
Sf
V
CC
= 4.0 to
5.5 V
— — 250 ns
— — 300