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Rev. 1.0, 07/01, page
viii
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xxiv
3.4.1 External Interrupts ...............................................................................................50
3.4.2 Internal Interrupts ................................................................................................51
3.4.3 Interrupt Handling Sequence ...............................................................................52
3.4.4 Interrupt Response Time......................................................................................53
3.5 Usage Notes......................................................................................................................55
3.5.1 Interrupts after Reset............................................................................................55
3.5.2 Notes on Stack Area Use .....................................................................................55
3.5.3 Notes on Rewriting Port Mode Registers.............................................................55
Section 4 Address Break....................................................................................57
4.1 Register Descriptions........................................................................................................57
4.1.1 Address Break Control Register(ABRKCR) .......................................................58
4.1.2 Address Break Status Register(ABRKSR) ..........................................................59
4.1.3 Break Address Registers (BARH, BARL)...........................................................59
4.1.4 Break Data Registers (BDRH, BDRL) ................................................................60
4.2 Operation ..........................................................................................................................60
Section 5 Clock Pulse Generators .....................................................................63
5.1 System Clock Generator ...................................................................................................63
5.1.1 Connecting a Crystal Oscillator...........................................................................64
5.1.2 Connecting a Ceramic Oscillator.........................................................................65
5.1.3 External Clock Input Method...............................................................................65
5.2 Subclock Generator...........................................................................................................65
5.2.1 Connecting a 32.768-kHz Crystal Oscillator .......................................................66
5.2.2 Pin Connection when Not Using Subclock..........................................................66
5.3 Prescalers ..........................................................................................................................67
5.3.1 Prescaler S............................................................................................................67
5.3.2 Prescaler W..........................................................................................................67
5.4 Usage Notes......................................................................................................................67
5.4.1 Note on Oscillators ..............................................................................................67
5.4.2 Notes on Board Design........................................................................................68
Section 6 Power-down Modes...........................................................................69
6.1 Register Descriptions........................................................................................................69
6.1.1 System Control Register 1(SYSCR1)..................................................................69
6.1.2 System Control Register 2(SYSCR2)..................................................................71
6.1.3 Module Standby Control Register 1(MSTCR1) ..................................................72
6.2 Mode Transitions and States of the LSI............................................................................73
6.2.1 Sleep Mode..........................................................................................................76
6.2.2 Standby Mode......................................................................................................77
6.2.3 Subsleep Mode.....................................................................................................77
6.2.4 Subactive Mode ...................................................................................................78
6.3 Operating Frequency in the Active Mode.........................................................................78