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CHAPTER9 DEVICES
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9.6 Index Register (Z)/Standard Device Resister (Z)
9.6.1 Index register (Z)
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(b) When using the index register for a 32-bit instruction
The processing target is Zn and Zn+1.
The lower 16 bits correspond to the specified index register number (Zn), and the higher 16 bits correspond to
the specified index register number + 1.
When Z2 is specified in the DMOV instruction, Z2 represents the lower 16 bits and Z3 represents
the higher 16 bits. (The most significant bit in a 32-bit structure is a sign bit.)
(3) When using 32-bit index modification
For the file register (ZR), extended data register (D), extended link register (W) using the serial number access
method, 32-bit index modification using two points of the index register is available.
The following two kinds of methods can be used to specify the index register.
• Specify the range used for 32-bit index modification.
• Specify the 32-bit index modification using "ZZ".
Note9.3Note1
Remark
For details and precautions of index modification using the index register, refer to the following.
QCPU Programming Manual (Common Instructions)
Figure 9.61 Data transfer with a 32-bit instruction and storage location
Note1
Example
D0
Z2
DMOV
Z3 Z2
Processing target:
Upper 16 bits Lower 16 bits
Note9.3
When specifying the 32-bit index modification using "ZZ" for the Q02UCPU, Q03UDCPU, Q04UDHCPU,
Q06UDHCPU, Q13UDHCPU, or Q26UDHCPU, check the versions of the CPU module and GX Developer.
( Appendix 2)
Universal