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APPEN-
DIX
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Appendix 3 Method of Replacing Basic Model QCPU or High Performance Model QCPU with Universal
Model QCPU
Appendix 3.4 Functions
APPENDICES
App - 53
[Ladder mode] [List mode]
In Example 2, in the ladder block starting from the step 15, the AND<> instruction of the step 17 or 21 is supposed
to be not executed when M0 (valid data flag) is off.
However, since the LD instruction which is always executed is used in the step 16 and 20, the AND<> instruction
of the step 17 or 21 is executed regardless of the execution status of the LD instruction in the step 15 when M1 or
M2 is on.
For this reason, even when M0 is off, if the D10Z1 value is outside the D device range, "OPERATION ERROR"
(error code: 4101) will be detected in the AND<> instruction of the step 17.
Note that the step 26 (MOV D0 D1) and the step 28 (INC D2) are not executed.
For the method of avoiding "OPERATION ERROR" (error code: 4101), refer to (2) in this section.
[Ladder mode] [List mode]
In Example 3, the AND<> instruction of the step 16 is not executed when M0 (valid data flag) of the step 15 is off.
For this reason, "OPERATION ERROR" (error code: 4101) will not be detected no matter what the D10Z1 value
is.
Example 2) Detecting "OPERATION ERROR" (error code: 4101)
Example 3) Not detecting "OPERATION ERROR" (error code: 4101)