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Specifying the
JClock
If you remember from "What’s a State Analyzer" in Feeling Comfortable
With Logic Analyzers, the state analyzer samples the data under the control
of an external clock which is "synchronous" with your circuit under test.
Therefore, you must specify which clock probe you will use for your
measurement. In this exercise, you will use the J clock which is accessible
through pod 1.
1. Display the State Format Specification menu.
2. Set the J Clock to sample on a negative-going edge.
a. Touch the field labeled Clock.
Figure 8-9. Clock Selection
Using the State Analyzer HP 16510B
8 - 10 Front-Panel Reference