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68020 CPU Package: 114-pin PGA
Accessories Required: HP 10313G
Maximum Clock Speed: 25 MHz clock input
Signal Line Loading: 100 KΩ +10pFonanyline
Microprocessor Cycles Identified: User data read/write
User program read
Supervisor read/write
Supervisor program read
Bus Grant
CPU space accesses including:
Breakpoint acknowledge
Access level control
Coprocessor communication
Interrupt acknowledge
Additional Capabilities: The logic analyzer captures all bus cycles,
including prefetches. The 68020
microprocessor must be operating with the
internal cache memory disabled for the logic
analyzer to provide inverse assembly.
Maximum Power Required: None
Number of Probes Used: Five 16-channel probes
HP 16510B Microprocessor Specific Measurements
Front-panel Reference 14 - 15