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DEFINITY ECS Release 8.2 Maintenance for R8.2csi
555-233-119 Issue 1
April 2000
Maintenance Objects
3-972PROCR (RISC Processor Circuit Pack TN798)
3
Processor Cache Test (#895)
This test is a nondestructive test. This test overwrites the contents in the
Instruction and Data Caches, requiring them to be refilled during normal
execution.
This test verifies that the Processor Instruction and Data Caches are functional.
Some errors in the caches will simply reduce performance by forcing instructions
or data to be read from memory more often than would normally be necessary. In
any case, cache problems are serious and the Processor circuit pack must be
replaced as soon as possible if they are detected.
Table 3-425. Test #82 Processor Bus Time-out Exception Test
Error
Code
Test
Result Description/ Recommendation
100 ABORT The test did not complete within the allowable time period.
2500 ABORT Internal system error
1. Retry the command.
FAIL The interrupt was not detected or acted upon.
1. Repeat the command at 1-minute intervals a maximum of 5 times.
2. If the test continues to fail, the Processor circuit pack should be
replaced. The replacement must have enough memory for this system.
PASS The interrupt was correctly detected. The RISC Processor is functioning
correctly.
Continued on next page
Table 3-426. Test #895 Processor Cache Test
Error
Code
Te st
Result Description/ Recommendation
100 ABORT The test did not complete within the allowable time period.
1. Retry the command.
2500 ABORT Internal system error
1. Retry the command.
FAIL The Processor cache is not functioning correctly.
1. Replace the Processor circuit pack immediately.
PASS The cache portion of the Processor circuit pack is operating correctly.
Continued on next page