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DEFINITY ECS Release 8.2 Maintenance for R8.2csi
555-233-119 Issue 1
April 2000
Maintenance Objects
3-1000SW-CTL (Switch Control)
3
Control Channel Transmission Test (#94)
Control channel messages are sent from the SPE to selected port circuit packs
and the response from the port circuit packs is checked. This tests the ability of
the Switch Control to send and receive messages on the control channel of the
TDM Bus.
Table 3-443. TEST #93 Switch Control Reset Test
Error
Code
Te s t
Result Description/ Recommendation
2012 ABORT Internal system error
2013
2100
none
ABORT Could not allocate the necessary system resources to run this test.
1. Retry the command at 1-minute intervals a maximum of 5 times.
2000 or
None
FAIL The Switch Control could not be successfully reset. If this is a standard
system, the customer probably cannot make or receive calls.
1. This failure could be due to either a Processor circuit pack failure or the
loss of system timing signals. If the Switch Control is alarmed, then
suspect a Processor circuit pack failure. If the Switch Control is not
alarmed, investigate the possible loss of system timing signals. See
“TDM Bus Clock”. If many port circuit pack LEDs are lit, suspect a TDM
Bus Clock problem. If only the Processor circuit pack LED is lit, suspect
the Processor circuit pack. If the Processor circuit pack is determined
to be at fault, proceed to Step 2.
2. If calls cannot be made, replace the Processor board.
PASS The Switch Control has initialized correctly. Look at results of the other tests
to see if it is operating correctly.
Continued on next page
Table 3-444. TEST #94 Control Channel Transmission Test
Error
Code
Te st
Result Description/ Recommendation
0 ABORT The port circuit packs necessary for this test are not available.
1. Retry the command at 1-minute intervals a maximum of 5 times.
2. If the test continues to abort, then replace the Processor circuit pack.
Continued on next page